This post was originally published on Classiq's Blog on September 5th, 2023. Subscribe to the Classiq blog and mine, for more deep dives about the Classiq platform!
Quantum computing aims to revolutionize industries and tackle problems considered intractable by classical computers, such as helping create better materials to withstand heat and strain for better materials, batteries, and energy technologies. However, building large-scale quantum computers brings many challenges, from creating scalable quantum bit (qubit) architectures to increasing the time quantum information is stored.
Quantum computing processors have already hit the number of qubits where classical simulation of quantum systems is no longer possible. We are in the era of Noisy Intermediate-Scale Quantum (NISQ) devices. These devices have up to a few thousand imperfect qubits, which limits the number of gates we can sequentially run in a quantum processor.
So, optimizing software performance for imperfect hardware is critical for the performance of quantum systems. Certain algorithms are more effective on certain quantum hardware architectures and benefit massively by carefully placing gates on specific qubits. This optimization could be the key to quantum advantage. The same algorithm, unoptimized, might do absolutely nothing. But this requires hardware awareness.
Co-design, a strategy that designs hardware and software simultaneously, will speed up quantum tech's evolution. This strategy aims to overcome the limitations that developers might face in isolation and to bridge this chasm, facilitating a seamless integration that allows software and hardware to be developed together (in superposition? ha! ha!) to bring quantum advantage to the real world.
GRIDLOCKS IN QUANTUM ADVANTAGE
A significant challenge in the growth of quantum computing’s potential is the gap in communications of the software-to-hardware, or vice versa, pipeline. Everyone in quantum development, hardware and software, needs to think full-stack.
On the quantum hardware development side, building a chip requires manual effort to tailor specific hardware architectures with practical quantum algorithms for the best possible performance on NISQ devices. Unfortunately, this is time-intensive and needs expertise in microfabrication, electrical engineering, physics, and software engineering. Additionally, tradeoffs are made for generalizability, allowing more classes of algorithms to be run on any chip while pushing the optimization work onto software developers.
On the software side, developing algorithms in isolation is great for theory and expanding the breadth of problems quantum computers may eventually solve, but without hardware awareness, there is no advantage. Therefore, there’s a gridlock in development because the top-down design approach leads to trying to fit a square peg into various round holes. Some may fit fine – but advancing quantum technology can be much more effective.
TOP-DOWN QUANTUM DESIGN
The traditional top-down approach for researchers in quantum computing starts with high-level design. This design is usually a quantum algorithm described in an abstract, high-level language like Python. These instructions can then be converted into quantum circuits, or gates, placed on each qubit. Classiq's advanced algorithmic approach can drastically reduce the time and complexity of quantum circuit development. In minutes, you can have thousands of lines of code to start tweaking for your quantum chemistry problem, quickly allowing you to write new experiments instead of spending your time doing re-writes of the same circuits for IBM, Quantinuum, and IonQ by hand.
But then you realize – you can’t just map the same code to the different quantum systems. The basis gates for the hardware backends are different. The connectivities range from all-to-all to linear. The gate execution times vary.
Sometimes, you even find that Qubit 5 is dead on the chip. Too bad that Qubit 5 is used a lot in your code. You sigh, make another cup of coffee, and settle in for a long weekend of code refactoring.
That’s where compilers and transpilers can save your day.
COMPILATION AND TRANSPILATION ONTO REAL QUANTUM HARDWARE
The generated circuit is not the circuit that is actually applied to the quantum hardware. Here is where the hardware awareness needs to begin. This high-level, hardware-agnostic quantum algorithm must be synthesized (compiled) and translated (transpiled) to instructions compatible with specific quantum hardware. This process converts written circuits into the correct basis gates and optimizes them for the hardware actually used.
The efficiency of these quantum circuits depends on intricate trade-offs. To optimize quantum algorithms you need to make decisions based on available resources and constraints. For instance, different possible implementations of a Multi-Controlled Toffoli (MCX) gate, which is used in the Grover operator, logical AND, and state preparation, depend on factors such as the number of qubits, auxiliary qubits, the connectivity map, and the circuit depth.
While we can increase state preparation accuracy by allowing for longer circuits with increased qubits, in reality, we may need to opt for shorter circuits or fewer qubits at reduced accuracy. In the Option Pricing synthesis model on Classiq’s platform, we can choose a max circuit width (the number of qubits used), a max circuit depth (number of gates in a row allowed), or even the total number of gates. Or, we can simply choose to optimize for the minimum width or depth and let Classiq’s software handle the tradeoffs with its’ automated synthesis and compilation capabilities.
Once the compilation process is complete, transpilation is the next optimization loop. It takes the synthesized circuit and matches it to the desired hardware. These optimizations include combining a sequence of gates into an equivalent single gate and transformations such as qubit routing.
One example of qubit routing, an important software optimization for transpilers, is the reduction of SWAP gates. SWAP gates swap two quantum states and are used to increase the effective connectivity of quantum circuits and decrease qubit distance limitations. For example, if Qubit 1 and 3 have Qubit 4 in between them, as in the hardware map below, and we need to do a 2-qubit gate on Qubit 1 and 3, we first need to do a SWAP operation to get the quantum states next to each other. We’d need to apply a SWAP gate to 1 and 4, or to 3 and 4, before applying the 2-qubit gate.
However, SWAP gates can also increase circuit depth (the number of gates in a row on a qubit). Due to the short coherence times of qubits, adding depth means adding execution time and operations that can lead to more accumulated errors. Making quantum circuits more efficient often means minimizing these gates' use without sacrificing computational efficacy.
As you can imagine, keeping track of these quantum states as they grow larger becomes a challenging organizational problem for anyone. Classiq's unique capabilities include automatically generating high-quality, hardware-tailored quantum circuits.
For example, if you have a quantum algorithm initially composed with rotation gates RX, RY, and RZ gates, transpiling this circuit to run on a specific quantum computer may require converting these gates into the gates supported by the hardware.
The circuit diagram can provide insights into the model's overarching structure. In the Classiq platform, you can specify the backend service provider, the backend name, and the basis gates. Analyzing these visualizations in the platform and their corresponding transpiled versions on different hardware can lead to more hardware-efficient designs.
Great! You now have a tool that can transpile code effectively onto available hardware and let you develop optimized circuits in a fraction of the time gate-level modeling requires.
You have optimized your code for the hardware that’s available. With Classiq, you’ve saved weeks of time by adjusting the parameters on a high level and using your time to get the best performance out of your new algorithm with the available hardware.
CONNECTIVITY MAPS BRIDGE DESIGN PROBLEMS
The lingering question is: what if we could design an ideal chip optimized for the software instead of constantly adjusting the software to fit pre-existing hardware? We're not just envisioning a simulated environment with full qubit connectivity but imagining a tangible, real-world chip optimized for the algorithm.
For example, for a simple European option pricing experiment, we have this high-level algorithm:
You get a hardware-aware and optimized circuit using two qubits on an IBM 5 qubit processor, which can be accessed on Classiq’s platform by generating credentials for free at IBM Quantum. Because only certain qubits can act as a target or control gate in a CNOT, we have to SWAP:
But as you’re analyzing the circuit for your quantum algorithm, you see a few possible avenues for improvement. Maybe adding an extra qubit would reduce SWAP gates. Or, for this specific case, adding another basis gate would reduce the circuit and execution time by orders of magnitude.
By adding a single Z hardware gate, you reduce the maximum number of gates on one qubit from 18 to 3 and completely eliminate 2 qubit gates. You now have 4 total gates, making the execution time 10x faster. You can maybe even get to quantum advantage today.
Recognizing the gap between top-down and bottom-up methodologies, Classiq introduces the connectivity map. This isn't just any map; it's a strategic bridge across the software-hardware divide.
A connectivity map for quantum computers describes how the qubits are interconnected, which describes which quantum operations can occur between pairs of qubits. It represents the hardware architecture (or topology) of the quantum processor. The specific layout of the connectivity can influence the efficiency and possibility of running quantum algorithms, as specific algorithms might need multiple qubits to interact frequently. If direct interactions are not possible, intermediary gates, like SWAP gates, and additional qubits might be required, introducing overhead in error correction, circuit length, and even affecting chip size.
Understanding and optimizing the connectivity map is vital for efficient quantum circuit design and compilation. In practice, these maps help quantum programmers and compilers optimize the placement of quantum operations, effectively using the hardware and potentially improving quantum algorithms' overall performance.
But what if you flip the script and use the connectivity map as a factor in algorithmic research and design instead of an afterthought?
Imagine the power of a connectivity map that understands both the high-level software design and the nuances of the physical chip. By aligning the software's requirements with the chip's capabilities from the get-go, there's potential for unprecedented efficiency. This means algorithms can be crafted with a clear understanding of the hardware’s constraints, and likewise, chips can be designed with specific quantum algorithms in mind.
Therefore, using the Classiq platform, you can synthesize the circuit for hardware not available in the Classiq platform – even the ideal real-world chip you’d want to have for your problem. You can specify the custom settings of the desirable hardware. This includes the basis gate set and the connectivity map of the hardware.
The benefits of an integrated approach are dual. Firstly, it creates more efficient quantum algorithms since software developers would better understand the hardware's capabilities and limitations. Secondly, hardware designers can create quantum chips specifically tailored to run certain algorithms, leading to better performance and potentially faster quantum computations. The future of software co-design and hardware optimization in quantum computing looks exceptionally promising with this bridge to make quantum technology truly “full-stack.”
THE FUTURE OF FULL-STACK QUANTUM COMPUTING
As Classiq and similar platforms mature, the field will likely see more integration between quantum algorithms and hardware development. This approach seems to maximize the potential of quantum technologies by enabling a faster development process, bringing us closer to reaching the transformative potential of quantum computing.
By starting at high-level design, automating the compilation and transpilation of quantum circuits, and integrating custom connectivity maps, all while opening access to quantum hardware through many hardware providers, Classiq’s tools empower researchers to optimize algorithms for specific hardware architectures to enhance overall efficiency, gain invaluable insights into quantum circuits, and visualize how algorithms perform on various hardware.
Free access is available to all by signing up for the Classiq platform here. Please share your experiences, feedback, and success stories with Classiq by joining the Slack community and contacting the Classiq team here. These real-world examples can inspire others and show the impact of co-design and hardware optimization, providing collaboration prospects between quantum software and hardware efforts. This is a big step towards a new era of quantum technologies that will revolutionize many industries and solve complex problems beyond the capabilities of classical computing.